{"id":4208,"date":"2024-05-30T17:53:46","date_gmt":"2024-05-30T09:53:46","guid":{"rendered":"https:\/\/www.hotchip.com.cn\/?post_type=product&p=4208"},"modified":"2024-08-15T10:29:51","modified_gmt":"2024-08-15T02:29:51","slug":"pb6158b","status":"publish","type":"product","link":"https:\/\/www.hotchip.com.cn\/pb6158b\/","title":{"rendered":"\u9ad8\u6548\u540c\u6b65\u53cc\u5411\u964d\u538b\u5145\u7535\u5668\u4e0eI2C\u63a5\u53e3\u7684\u63a7\u5236\u5668PB6158B"},"content":{"rendered":"
1\u3001\u89c4\u683c\u53c2\u6570<\/strong><\/p>\n TJ=25\u00b0C\uff0cVBUS=5V\uff0cVBAT=10.8V\uff0c\u9664\u975e\u53e6\u6709\u8bf4\u660e\u3002<\/p>\n PSTOP = L, \u975e\u4ea4\u6362\u7684<\/td>\n PSTOP = L, \u5145\u7535\u7ec8\u6b62\u540e<\/td>\n AD_START = 1<\/td>\n VBUS = 5V, VCC = 4V<\/td>\n VCELL_SET = 000~1111, TRICKLE_SET = 0<\/td>\n VCELL_SET = 000~1111, TRICKLE_SET = 1<\/td>\n V<\/td>\n<\/tr>\n VINREG_RATIO = 0<\/td>\n 14.7<\/td>\n 15<\/td>\n 15.3<\/td>\n V<\/td>\n<\/tr>\n VINREG_SET=0x6F, VINREG_RATIO = 1<\/td>\n 4.4<\/td>\n 4.5<\/td>\n 4.6<\/td>\n V<\/td>\n<\/tr>\n VBUSREF_E_REF target from 0.5V to 2.048V<\/td>\n VBUS_RATIO = 1 (5x) VBUS = 3.6 ~10.24V<\/td>\n VBUS_RATIO = 0 (12.5x) VBUS = 9 ~ 24V<\/td>\n VBUSREF_E_SET = 1V<\/td>\n IBUS_RATIO=01(6x) IBUS_LIM = 0x7F<\/td>\n -10%<\/td>\n 10%<\/td>\n IBUS_LIM = 0x7F<\/td>\n IBUS_RATIO = 01 (6x) IBUS_LIM = 0x7F<\/td>\n IBUS_RATIO = 10 (3x) IBUS_LIM = 0x7F<\/td>\n IBAT_LIM = 0xFF<\/td>\n IBAT_RATIO = 1 (12x) IBAT_LIM = 0xFF<\/td>\n 2\u3001\u4ea7\u54c1\u7279\u6027<\/b><\/strong><\/p>\n 3\u3001\u5178\u578b\u5e94\u7528\u7535\u8def\u56fe<\/strong><\/p>\n <\/p>\n 4\u3001\u7ba1\u811a\u56fe\u53ca\u529f\u80fd\u8bf4\u660e<\/strong><\/p>\n\n\n
\n \u7b26\u53f7<\/strong><\/td>\n \u53c2\u6570<\/strong><\/td>\n \u6d4b\u8bd5\u6761\u4ef6<\/strong><\/td>\n \u6700\u5c0f\u503c<\/strong><\/td>\n \u5178\u578b\u503c<\/strong><\/td>\n \u6700\u5927\u503c<\/strong><\/td>\n \u5355\u4f4d<\/strong><\/td>\n<\/tr>\n \n \u00a0\u7535\u6e90\u7535\u538b<\/td>\n<\/tr>\n \n VUVLO_VBUS<\/td>\n VBUS\u6b20\u538b\u9501\u5b9a<\/td>\n \u4e0a\u5347<\/td>\n <\/td>\n 2.5<\/td>\n 2.7<\/td>\n V<\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n \u5ef6\u8fdf<\/td>\n <\/td>\n 170<\/td>\n <\/td>\n mV<\/td>\n<\/tr>\n \n VUVLO_VBAT<\/td>\n VBAT\u6b20\u538b\u9501\u5b9a\u9608\u503c<\/td>\n \u4e0a\u5347<\/td>\n <\/td>\n 2.4<\/td>\n 2.6<\/td>\n V<\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n \u5ef6\u8fdf<\/td>\n <\/td>\n 170<\/td>\n <\/td>\n mV<\/td>\n<\/tr>\n \n IQ_VBAT<\/td>\n \u9759\u6b62\u7535\u6d41\u8fdb\u5165VBAT<\/td>\n VBUS = 5V<\/p>\n <\/td>\n 2.4<\/td>\n 4<\/td>\n mA<\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n VBUS = 5V<\/p>\n <\/td>\n 2.4<\/td>\n 4<\/td>\n mA<\/td>\n<\/tr>\n \n IQ_VBUS<\/td>\n \u9759\u6b62\u7535\u6d41\u8fdb\u5165VBUS<\/td>\n PSTOP = L, \u975e\u4ea4\u6362\u7684<\/td>\n <\/td>\n 40<\/td>\n <\/td>\n \u03bcA<\/td>\n<\/tr>\n \n ISB_VBAT<\/td>\n \u5f85\u673a\u7535\u6d41\u8fdb\u5165VBAT<\/td>\n VBUS\u6253\u5f00 PSTOP = H, AD_START = 0<\/td>\n <\/td>\n 40<\/td>\n <\/td>\n \u03bcA<\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n VBUS open PSTOP = H,<\/p>\n <\/td>\n 0.65<\/td>\n 1.2<\/td>\n mA<\/td>\n<\/tr>\n \n ISB_VBUS<\/td>\n \u5f85\u673a\u7535\u6d41\u8fdb\u5165VBUS<\/td>\n PSTOP = H, AD_START =0<\/td>\n <\/td>\n 40<\/td>\n <\/td>\n \u03bcA<\/td>\n<\/tr>\n \n ISD_VBAT<\/td>\n \u5173\u95ed\u7535\u6d41\u5230VBAT<\/td>\n \/CE = H, VBUS = open<\/td>\n <\/td>\n 35<\/td>\n <\/td>\n \u03bcA<\/td>\n<\/tr>\n \n VDRV\u3001\u62e8\u548c\u7535\u6e90\u5f00\u5173<\/td>\n<\/tr>\n \n VDRV<\/td>\n \u5173\u95ed\u7535\u6d41\u5230VBAT<\/td>\n PSTOP = L, VBUS = 9V<\/td>\n 5.75<\/td>\n 6<\/td>\n 6.25<\/td>\n V<\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n PSTOP = L, VBUS = 5V<\/td>\n 4.95<\/td>\n 4.98<\/td>\n 5<\/td>\n V<\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n PSTOP = H<\/td>\n <\/td>\n <\/td>\n 2<\/td>\n V<\/td>\n<\/tr>\n \n IVDRV_LIM<\/td>\n VDRV\u7535\u6d41\u9650\u5236<\/td>\n PSTOP = L<\/p>\n <\/td>\n 45<\/td>\n <\/td>\n mA<\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n PSTOP = H<\/td>\n <\/td>\n <\/td>\n 1<\/td>\n mA<\/td>\n<\/tr>\n \n RHS\/LS_PU<\/td>\n \u9ad8\/\u4f4e\u4fa7MOS\u9a71\u52a8\u7a0b\u5e8f\u4e0a\u62c9\u7535\u963b\u7bb1<\/td>\n <\/td>\n <\/td>\n 4<\/td>\n <\/td>\n \u03a9<\/td>\n<\/tr>\n \n RHS\/LS_PD<\/td>\n \u9ad8\/\u4f4e\u4fa7MOS\u9a71\u52a8\u7a0b\u5e8f\u4e0b\u62c9\u7535\u963b\u5668<\/td>\n <\/td>\n <\/td>\n 1<\/td>\n <\/td>\n \u03a9<\/td>\n<\/tr>\n \n VLDO\uff0c\u5355\u7247\u673a\u7684\u7535\u6e90<\/td>\n<\/tr>\n \n VLDO<\/td>\n VLDO\u8c03\u8282\u7535\u538b<\/td>\n <\/td>\n <\/td>\n 3.3<\/td>\n <\/td>\n V<\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n <\/td>\n <\/td>\n 3.0<\/td>\n <\/td>\n V<\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n <\/td>\n <\/td>\n 5.0<\/td>\n <\/td>\n V<\/td>\n<\/tr>\n \n ILDO<\/td>\n VLDO\u7535\u6d41\u9650\u5236<\/td>\n VBUS=5V, VLDO=3.3V<\/td>\n <\/td>\n 10<\/td>\n <\/td>\n mA<\/td>\n<\/tr>\n \n \u5145\u7535\u6a21\u5f0f\u4e0b\u7684\u53c2\u8003\u7535\u538b<\/td>\n<\/tr>\n \n VBATS_int<\/td>\n \u5185\u90e8\u8bbe\u7f6e\u7684VBATS\u7cbe\u5ea6\uff0c\u8d85\u8fc7VBATS\u76ee\u6807<\/td>\n VCELL_SET=000~111<\/td>\n -0.5<\/td>\n <\/td>\n 0.5<\/td>\n %<\/td>\n<\/tr>\n \n VTRICKLE_int<\/td>\n \u5185\u90e8\u8bbe\u7f6e\u7684\u6d93\u6d41\u5145\u7535\u9608\u503c\u7535\u538b<\/td>\n Cell number = N<\/p>\n 2.73* N<\/td>\n 2.94* N<\/td>\n 3.15* N<\/td>\n V<\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n Cell number = N<\/p>\n 2.31* N<\/td>\n 2.52* N<\/td>\n 2.73* N<\/td>\n <\/p>\n \n VEOC<\/td>\n EOC\u7535\u538b\u9608\u503c\uff0c\u8d85\u8fc7VBAT\u76ee\u6807<\/td>\n <\/td>\n 97%<\/td>\n 98%<\/td>\n 99%<\/td>\n <\/td>\n<\/tr>\n \n VRECH<\/td>\n \u91cd\u65b0\u5145\u7535\u9608\u503c\u7535\u538b\uff0c\u8d85\u8fc7VBAT\u76ee\u6807<\/td>\n <\/td>\n 94.8%<\/td>\n 95.8%<\/td>\n 96.8%<\/td>\n <\/td>\n<\/tr>\n \n VINREG<\/td>\n VINREG\u53c2\u8003\u7535\u538b<\/td>\n 4.5V target VINREG_SET = 0x2C,VINREG_RATIO = 0<\/td>\n 4.3<\/td>\n 4.5<\/td>\n 4.7<\/td>\n V<\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n 15V target VINREG_SET = 0x95,<\/p>\n <\/p>\n <\/p>\n <\/p>\n <\/p>\n \n <\/td>\n <\/td>\n 4.48V target<\/p>\n <\/p>\n <\/p>\n <\/p>\n <\/p>\n \n <\/td>\n <\/td>\n 10V target VINREG_SET = 0xF9,VINREG_RATIO = 1<\/td>\n 9.8<\/td>\n 10<\/td>\n 10.2<\/td>\n V<\/td>\n<\/tr>\n \n VBAT_OVP<\/td>\n VBAT OVP\u9608\u503c\uff0c\u8d85\u8fc7VBAT\u76ee\u6807<\/td>\n VBAT_SEL = 0\/1<\/td>\n 107%<\/td>\n 110%<\/td>\n 112%<\/td>\n <\/td>\n<\/tr>\n \n VCLAMP<\/td>\n <\/td>\n <\/td>\n <\/td>\n 125<\/td>\n <\/td>\n mV<\/td>\n<\/tr>\n \n \u5145\u7535\u6a21\u5f0f\u4e0b\u7684\u53c2\u8003\u7535\u538b<\/td>\n<\/tr>\n \n VFB<\/td>\n \u5916\u90e8\u8bbe\u7f6e\u65f6\u7684FB\u53c2\u8003\u7535\u538b<\/td>\n FB_SEL = 1,<\/p>\n -2%<\/td>\n <\/td>\n 2%<\/td>\n <\/td>\n<\/tr>\n \n VBUS<\/td>\n \u5185\u90e8\u8bbe\u7f6e\u7684VBUS\u53c2\u8003\u7535\u538b\u7cbe\u5ea6<\/td>\n FB_SEL = 0<\/p>\n -2%<\/td>\n <\/td>\n 2%<\/td>\n <\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n FB_SEL = 0<\/p>\n -2%<\/td>\n <\/td>\n 2%<\/td>\n <\/td>\n<\/tr>\n \n VBUS_OVP<\/td>\n VBUS OVP\u9608\u503c\uff0c\u4e0a\u5347\u8fb9\u7f18<\/td>\n VBUSREF_I_SET = 1V<\/p>\n 107.3%<\/td>\n 110%<\/td>\n 113%<\/td>\n <\/td>\n<\/tr>\n \n <\/td>\n \u6ede\u540e\u4f5c\u7528<\/td>\n VBUSREF_I_SET = 1V VBUSREF_E_SET = 1V<\/td>\n <\/td>\n 3%<\/td>\n <\/td>\n <\/td>\n<\/tr>\n \n CURRENT LIMIT<\/td>\n<\/tr>\n \n IBUS_LIM<\/td>\n IBUS\u7535\u6d41\u9650\u5236\u7cbe\u5ea6<\/td>\n \u5145\u7535\u65b9\u5f0f, 6A target<\/p>\n <\/p>\n <\/td>\n <\/p>\n <\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n \u5145\u7535\u65b9\u5f0f, 3A target IBUS_RATIO = 10 (3x)<\/p>\n -10%<\/td>\n <\/td>\n 10%<\/td>\n <\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n \u653e\u7535\u65b9\u5f0f, 6A target<\/p>\n -10%<\/td>\n <\/td>\n 10%<\/td>\n <\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n \u653e\u7535\u65b9\u5f0f, 3A target<\/p>\n -10%<\/td>\n <\/td>\n 10%<\/td>\n <\/td>\n<\/tr>\n \n IBAT_LIM<\/td>\n IBAT\u7535\u6d41\u9650\u5236\u7cbe\u5ea6<\/td>\n \u5145\u7535\u65b9\u5f0f, 6A target IBAT_RATIO = 0 (6x)<\/p>\n -10%<\/td>\n <\/td>\n 10%<\/td>\n <\/td>\n<\/tr>\n \n <\/td>\n <\/td>\n \u5145\u7535\u65b9\u5f0f, 12A target<\/p>\n -10%<\/td>\n <\/td>\n 10%<\/td>\n <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n \n